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femtoclocks? crystal-to-lvds frequency synthesizer ics844001-21 idt ? / ics ? insert product name 1 ics844001ag-21 rev. a september 14, 2007 preliminary g eneral d escription the ics844001-21 is a a highly versatile, low phase noise lvds synthesizer which can generate low jitter reference clocks for a variety of communications applications and is a member of the hiperclocks tm family of high performance clock solutions from idt. the dual crystal interface allows the synthesizer to support up to two communications standards in a given application (i.e. 1gb ethernet with a 25mhz crystal and 1gb fibre channel using a 25.5625mhz crystal). the rms phase jitter performance is typically less than 1ps, thus making the device acceptable for use in demanding applications such as oc48 sonet and 10gb ethernet. the ics844001-21 is packaged in a small 24-pin tssop package. f eatures ? one differential lvds output pair and one lvcmos reference output ? selectable crystal oscillator interface or lvcmos/lvttl single-ended input ? vco range: 560mhz - 700mhz ? supports the following applications: sonet, ethernet, fibre channel, serial ata, and hdtv ? rms phase jitter @ 622.08mhz (12khz - 20mhz): 0.92ps (typical) ? full 3.3v supply mode ? 0c to 70c ambient operating temperature ? available in both standard (rohs 5) and lead-free (rohs 6) packages hiperclocks? ic s p in a ssignment 1 1 1 0 0 1 0 0 0 0 0 1 1 0 1 1 phase detector vco 000 18 001 22 010 24 011 25 100 32 (default) 101 40 110 40 111 40 n 000 1 001 2 010 3 011 4 (default) 100 5 101 6 110 8 111 10 m 3 3 osc osc ref_out q nq n2:n0 sel0 sel1 xtal_in0 xtal_out0 xtal_in1 xtal_out1 ref_clk mr ref_oe m2:m0 pulldown pulldown pulldown pulldown pulldown ics844001-21 24-lead tssop 4.40mm x 7.8mm x 0.92mm package body g package top view v ddo _ cmos n0 n1 n2 v ddo _ lvds q0 nq0 gnd v dda v dd xtal_out1 xtal_in1 1 2 3 4 5 6 7 8 9 10 11 12 ref_out gnd ref_oe m2 m1 m0 mr sel1 sel0 ref_clk xtal_in0 xtal_out0 24 23 22 21 20 19 18 17 16 15 14 13 b lock d iagram the preliminary information presented herein represents a product in pre-production. the noted characteristics are based on ini tial product characterization and/or qualification. integrated device technology, incorporated (idt) reserves the right to change any circuitry or specificat ions without notice.
idt ? / ics ? insert product name 2 ics844001ag-21 rev. a september 14, 2007 ics844001-21 femtoclocks? crystal-to-l vds frequency synthesizer preliminary t able 1. p in d escriptions t able 2. p in c haracteristics r e b m u ne m a ne p y tn o i t p i r c s e d 1v s o m c _ o d d r e w o p. t u p t u o s o m c v l r o f n i p y l p p u s t u p t u o 3 , 21 n , 0 nt u p n ip u l l u p . 4 t l u a f e d . s n i p t c e l e s r e d i v i d t u p t u o . s l e v e l e c a f r e t n i l t t v l / s o m c v l 42 nt u p n in w o d l l u p 5v s d v l _ o d d r e w o p. s t u p t u o s d v l r o f n i p y l p p u s t u p t u o 7 , 6q n , qt u p u o. s l e v e l e c a f r e t n i s d v l . r i a p t u p t u o l a i t n e r e f f i d 3 2 , 8d n gr e w o p. d n u o r g y l p p u s r e w o p 9v a d d r e w o p. n i p y l p p u s g o l a n a 0 1v d d r e w o p. n i p y l p p u s e r o c 1 1 2 1 , 1 t u o _ l a t x 1 n i _ l a t x t u p n i , t u p t u o e h t s i 1 t u o _ l a t x . e c a f r e t n i l a t s y r c t n a n o s e r l e l l a r a p . t u p n i e h t s i 1 n i _ l a t x 3 1 4 1 , 0 t u o _ l a t x 0 n i _ l a t x t u p n i , t u p t u o e h t s i 0 t u o _ l a t x . e c a f r e t n i l a t s y r c t n a n o s e r l e l l a r a p . t u p n i e h t s i 0 n i _ l a t x 5 1k l c _ f e rt u p n in w o d l l u p. s l e v e l e c a f r e t n i l t t v l / s o m c v l . t u p n i k c o l c e c n e r e f e r 7 1 , 6 11 l e s , 0 l e st u p n in w o d l l u p. s l e v e l e c a f r e t n i l t t v l / s o m c v l . s n i p t c e l e s x u m 8 1r mt u p n in w o d l l u p e r a s r e d i v i d l a n r e t n i e h t , h g i h c i g o l n e h w . t e s e r r e t s a m h g i h e v i t c a o t q n t u p t u o d e t r e v n i e h t d n a w o l o g o t q t u p t u o e u r t e h t g n i s u a c t e s e r e r a s t u p t u o e h t d n a s r e d i v i d l a n r e t n i e h t , w o l c i g o l n e h w . h g i h o g . s l e v e l e c a f r e t n i l t t v l / s o m c v l . d e l b a n e 0 2 , 9 11 m , 0 mt u p n in w o d l l u p . 2 3 t l u a f e d . s n i p t c e l e s r e d i v i d k c a b d e e f . s l e v e l e c a f r e t n i l t t v l / s o m c v l 1 22 mt u p n ip u l l u p 2 2e o _ f e rt u p n in w o d l l u p . w o l t l u a f e d . e l b a n e t u p t u o k c o l c e c n e r e f e r . s l e v e l e c a f r e t n i l t t v l / s o m c v l 4 2t u o _ f e rt u p t u o . s l e v e l e c a f r e t n i l t t v l / s o m c v l . t u p t u o k c o l c e c n e r e f e r : e t o n n w o d l l u p d n a p u l l u p . s e u l a v l a c i p y t r o f , s c i t s i r e t c a r a h c n i p , 2 e l b a t e e s . s r o t s i s e r t u p n i l a n r e t n i o t r e f e r l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u c n i e c n a t i c a p a c t u p n i 4f p r n w o d l l u p r o t s i s e r n w o d l l u p t u p n i 1 5k r p u l l u p r o t s i s e r p u l l u p t u p n i 1 5k r t u o e c n a d e p m i t u p t u ot u o _ f e r7
idt ? / ics ? insert product name 3 ics844001ag-21 rev. a september 14, 2007 ics844001-21 femtoclocks? crystal-to-l vds frequency synthesizer preliminary t able 3a. c ommon c onfigurations t able t u p n i e u l a v r e d i v i d me u l a v r e d i v i d n) z h m ( o c v y c n e u q e r f t u p t u o ) z h m ( n o i t a c i l p p a ) z h m ( k c o l c e c n e r e f e r 7 22 284 9 55 2 . 4 7v t d h 5 7 . 4 24 284 9 55 2 . 4 7v t d h 9 4 6 1 5 3 8 . 4 10 48 6 6 0 4 . 3 9 55 4 2 8 5 7 1 . 4 7v t d h 4 4 . 9 12 348 0 . 2 2 62 5 . 5 5 1t e n o s 4 4 . 9 12 388 0 . 2 2 66 7 . 7 7t e n o s 4 4 . 9 12 318 0 . 2 2 68 0 . 2 2 6t e n o s 4 4 . 9 12 328 0 . 2 2 64 0 . 1 1 3t e n o s 5 2 1 3 5 . 9 12 345 2 65 2 . 6 5 1e g i g 0 1 5 25 255 2 65 2 1e g i g 1 5 25 20 15 2 65 . 2 6e g i g 1 5 24 260 0 60 0 1s s e r p x e i c p 5 24 240 0 60 5 1a t a s 5 24 280 0 65 7a t a s 5 2 6 5 . 6 24 265 . 7 3 65 2 . 6 0 11 l e n n a h c e r b i f 5 2 6 5 . 6 24 235 . 7 3 65 . 2 1 2l e n n a h c e r b i f g i g 4 5 2 6 5 . 6 24 245 . 7 3 65 7 3 . 9 5 1l e n n a h c e r b i f g i g 0 1 5 2 . 1 38 135 . 2 6 55 . 7 8 1t e n r e h t e g i g 2 1 s t u p n i r e d i v i d m e u l a v ) z h m ( y c n e u q e r f t u p n i 2 m1 m0 mm u m i n i mm u m i x a m 000 8 11 . 1 39 . 8 3 00 1 2 25 . 5 28 . 1 3 010 4 23 . 3 22 . 9 2 011 5 24 . 2 2) t l u a f e d ( 0 . 8 2 10 0 2 35 . 7 19 . 1 2 10 1 0 40 . 4 15 . 7 1 t able 3b. p rogrammable m d ivider f unction t able t able 3c. p rogrammable n d ivider f unction t able s t u p n i e c n e r e f e re d o m l l p 1 l e s0 l e s 00 0 l a t x) t l u a f e d ( e v i t c a 01 1 l a t xe v i t c a 10 k l c _ f e re v i t c a 11 k l c _ f e rs s a p y b t able 3d. b ypass m ode f unction t able s t u p n i e u l a v e d i v i d n 2 n1 n0 n 000 1 00 1 2 010 3 011 ) t l u a f e d ( 4 10 0 5 10 1 6 110 8 111 0 1
idt ? / ics ? insert product name 4 ics844001ag-21 rev. a september 14, 2007 ics844001-21 femtoclocks? crystal-to-l vds frequency synthesizer preliminary t able 4a. p ower s upply dc c haracteristics , v dd = v ddo_lvds = v ddo_cmos = 3.3v5%, ta = 0c to 70c t able 4b. lvcmos / lvttl dc c haracteristics , v dd = v ddo_cmos = 3.3v5%, ta = 0c to 70c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h i e g a t l o v h g i h t u p n i 2v d d 3 . 0 +v v l i e g a t l o v w o l t u p n i 3 . 0 -8 . 0v i h i t u p n i t n e r r u c h g i h , 0 l e s , k l c _ f e r , f e r _ e o , 1 l e s 2 n , 1 m , 0 m , r m v d d v = n i v 5 6 4 . 3 =0 5 1a 1 n , 0 n , 2 mv d d v = n i v 5 6 4 . 3 =5a i l i t u p n i t n e r r u c w o l , 0 l e s , k l c _ f e r , f e r _ e o , 1 l e s 2 n , 1 m , 0 m , r m v d d v , v 5 6 4 . 3 = n i v 0 =5 -a 1 n , 0 n , 2 mv d d v , v 5 6 4 . 3 = n i v 0 =0 5 1 -a v h o ; e g a t l o v h g i h t u p t u o 1 e t o n t u o _ f e r6 . 2v v l o : e g a t l o v w o l t u p t u o 1 e t o n t u o _ f e r 5 . 0v 0 5 h t i w d e t a n i m r e t t u p t u o : 1 e t o n v o t s o m c _ o d d , n o i t c e s n o i t a m r o f n i t n e m e r u s a e m r e t e m a r a p e e s . 2 / . " m a r g a i d t i u c r i c t s e t d a o l t u p t u o v 3 . 3 " a bsolute m aximum r atings supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5v outputs, i o contin uous current 10ma surge current 15ma outputs, v o (lvcmos) -0.5v to v ddo + 0.5v package thermal impedance, ja 82.3c/w (0 mps) storage temperature, t stg -65c to 150c note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional op- eration of product at these conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for ex- tended periods may affect product reliability. l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v d d e g a t l o v y l p p u s e r o c5 3 1 . 33 . 35 6 4 . 3v v a d d e g a t l o v y l p p u s g o l a n av d d 5 1 . 0 ?3 . 3v d d v v s o m c _ , s d v l _ o d d e g a t l o v y l p p u s t u p t u o5 3 1 . 33 . 35 6 4 . 3v i d d t n e r r u c y l p p u s r e w o p 0 1 1a m i a d d t n e r r u c y l p p u s g o l a n a 5 1a m i s o m c _ , s d v l _ o d d t n e r r u c y l p p u s t u p t u o 0 4a m
idt ? / ics ? insert product name 5 ics844001ag-21 rev. a september 14, 2007 ics844001-21 femtoclocks? crystal-to-l vds frequency synthesizer preliminary t able 6. ac c haracteristics , v dd = v ddo_lvds = v ddo_cmos = 3.3v5%, ta = 0c to 70c t able 5. c rystal c haracteristics r e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u n o i t a l l i c s o f o e d o m l a t n e m a d n u fz h m y c n e u q e r f 2 10 4z h m ) r s e ( e c n a t s i s e r s e i r e s t n e l a v i u q e 0 5 e c n a t i c a p a c t n u h s 7f p l e v e l e v i r d 1w m . l a t s y r c t n a n o s e r l e l l a r a p f p 8 1 n a g n i s u d e z i r e t c a r a h c : e t o n t able 4c. lvds dc c haracteristics , v dd = v ddo_lvds = 3.3v5%, ta = 0c to 70c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f t u o y c n e u q e r f t u p t u o 6 50 0 7z h m t d p , y a l e d n o i t a g a p o r p 1 e t o n o t k l c _ f e r t u o _ f e r 5 9 . 2s n t ) ? ( t i j ; ) m o d n a r ( , r e t t i j e s a h p s m r 3 , 2 e t o n ) z h m 0 2 - z h k 2 1 ( z h m 8 0 . 2 2 62 9 . 0s p t r t / f t u p t u o e m i t l l a f / e s i r q n , q% 0 8 o t % 0 20 0 3s p t u o _ f e r% 0 8 o t % 0 20 0 3s p c d oe l c y c y t u d t u p t u o q n , q0 5% t u o _ f e r0 5% v e h t m o r f d e r u s a e m : 1 e t o n d d v o t t u p n i e h t f o 2 / s o m c _ o d d . t u p t u o e h t f o 2 / . l a t s y r c z t r a u q z h m 5 2 a g n i s u d e r u s a e m r e t t i j e s a h p : 2 e t o n . 5 6 d r a d n a t s c e d e j h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h t : 3 e t o n l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v d o e g a t l o v t u p t u o l a i t n e r e f f i d 0 0 4v m v d o v d o e g n a h c e d u t i n g a m 0 5v m v s o e g a t l o v t e s f f o 5 . 1v v s o v s o e g n a h c e d u t i n g a m 0 5v m
idt ? / ics ? insert product name 6 ics844001ag-21 rev. a september 14, 2007 ics844001-21 femtoclocks? crystal-to-l vds frequency synthesizer preliminary t ypical p hase n oise at 622.08mh z 622.08mhz rms phase jitter (random) 12khz to 20mhz = 0.92ps (typical) o ffset f requency (h z ) ? ? ? dbc hz n oise p ower phase noise result by adding sonet oc-12 filter to raw data raw phase noise data oc-12 filter
idt ? / ics ? insert product name 7 ics844001ag-21 rev. a september 14, 2007 ics844001-21 femtoclocks? crystal-to-l vds frequency synthesizer preliminary t pd v dd 2 v ddo_lvcmos 2 p arameter m easurement i nformation ref_out ref_clk rms p hase j itter lvds o utput r ise /f all t ime 3.3v lvds o utput l oad ac t est c ircuit lvcmos o utput r ise /f all t ime clock outputs 20% 80% 80% 20% t r t f v od p ropagation d elay phase noise mas k offset frequency f 1 f 2 phase noise plot rms jitter = area under the masked phase noise plot noise power 3.3v lvcmos o utput l oad ac t est c ircuit scope qx lvcmos gnd 1.655% -1.65v5% v dd , v ddo_cmos scope qx nqx 3.3v5% power supply +? float gnd lvds clock outputs 20% 80% 80% 20% t r t f 1.655% v dda v dd , v ddo_lvds v dda
idt ? / ics ? insert product name 8 ics844001ag-21 rev. a september 14, 2007 ics844001-21 femtoclocks? crystal-to-l vds frequency synthesizer preliminary d ifferential o utput v oltage s etup o ffset v oltage s etup ? ? ? 100 out out lv d s dc input v od / v od v dd out out lv d s dc input ? ? ? v os / v os v dd t pw t period t pw t period odc = x 100% q nq t period t pw t period odc = v ddo_cmos 2 x 100% t pw ref_out lvds o utput d uty c ycle /p ulse w idth /p eriod lvcmos o utput d uty c ycle /p ulse w idth /p eriod
idt ? / ics ? insert product name 9 ics844001ag-21 rev. a september 14, 2007 ics844001-21 femtoclocks? crystal-to-l vds frequency synthesizer preliminary a pplication i nformation as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. the ics844001-21 provides separate power supplies to isolate any high switching noise from the outputs to the internal pll. v dd , v dda , and v ddo_x should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. to achieve optimum jitter performance, power supply isolation is required. figure 1 illustrates how a 10 resistor along with a 10f and a 0.01 f bypass capacitor should be connected to each v dda . p ower s upply f iltering t echniques f igure 1. p ower s upply f iltering 10 v dda 10 f .01 f 3.3v .01 f v dd c rystal i nput i nterface the ics844001-21 has been characterized with 18pf parallel resonant crystals. the capacitor values shown in figure 2 below f igure 2. c rystal i npu t i nterface were determined using a 25mhz 18pf parallel resonant crystal and were chosen to minimize the ppm error. i nputs : c rystal i nputs for applications not requiring the use of the crystal oscillator input, both xtal_in and xtal_out can be left floating. though not required, but for additional protection, a 1k resistor can be tied from xtal_in to ground. ref_clk i nput for applications not requiring the use of the reference clock, it can be left floating. though not required, but for additional protection, a 1k resistor can be tied from the ref_clk to ground. lvcmos c ontrol p ins all control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. a 1k resistor can be used. r ecommendations for u nused i nput and o utput p ins o utputs : lvds o utput all unused lvds output pairs can be either left floating or terminated with 100 across. if they are left floating, there should be no trace attached. lvcmos o utput all unused lvcmos output can be left floating. there should be no trace attached. xtal_in xtal_out x1 18pf parallel crystal c1 22p c2 22p
idt ? / ics ? insert product name 10 ics844001ag-21 rev. a september 14, 2007 ics844001-21 femtoclocks? crystal-to-l vds frequency synthesizer preliminary 3.3v lvds d river t ermination a general lvds interface is shown in figure 4. in a 100 differential transmission line environment, lvds drivers require a matched load termination of 100 across near the receiver f igure 4. t ypical lvds d river t ermination input. for a multiple lvds outputs buffer, if only partial outputs are used, it is recommended to terminate the unused outputs. r1 100 3.3v 100 ohm differential transmission line 3.3v + - lvds lvcmos to xtal i nterface the xtal_in input can accept a single-ended lvcmos signal through an ac coupling capacitor. a general interface diagram is shown in figure 3. the xtal_out pin can be left floating. the input edge rate can be as slow as 10ns. for lvcmos inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. this configuration requires that the output f igure 3. g eneral d iagram for lvcmos d river to xtal i nput i nterface impedance of the driver (ro) plus the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the crystal input will attenuate the signal in half. this can be done in one of two ways. first, r1 and r2 in parallel should equal the transmission line impedance. for most 50 applications, r1 and r2 can be 100 . this can also be accomplished by removing r1 and making r2 50 . r2 zo = 50 vdd ro zo = ro + rs r1 vdd xtal _i n xtal _ou t .1uf rs
idt ? / ics ? insert product name 11 ics844001ag-21 rev. a september 14, 2007 ics844001-21 femtoclocks? crystal-to-l vds frequency synthesizer preliminary s chematic e xample figure 5 shows an example of ics844001-21 application schematic. in this example, the device is operated at v dd = 3.3v. the 18pf parallel resonant 25mhz crystal is used. the c1 = 22pf and c2 = 22pf are recommended for frequency accuracy. for different board layout, the c1 and c2 may be slightly adjusted for optimizing frequency accuracy. one example of lvds and one example of lvcmos terminations are shown in this schematic. the decoupling capacitors should be located as close as possible to the power pin. f igure 5. ics844001-21 s chematic l ayout
idt ? / ics ? insert product name 12 ics844001ag-21 rev. a september 14, 2007 ics844001-21 femtoclocks? crystal-to-l vds frequency synthesizer preliminary p ower c onsiderations this section provides information on power dissipation and junction temperature for the ics844001-21. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics844001-21 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v dd = 3.3v + 5% = 3.465v, which gives worst case results. core and lvds output power dissipation ? power (core, lvds) = v dd_max * (i dd + i ddo_lvds + i dda ) = 3.465v * (110ma + 40ma + 15ma) = 572mw lvcmos output power dissipation ? output impedance r out power dissipation due to loading 50 to v ddo_cmos /2 output current i out = v ddo_cmos_max / [2 * (50 + r out )] = 3.465v / [2 * (50 + 7 )] = 30.4ma ? power dissipation on the r out per lvcmos output power (r out ) = r out * (i out ) 2 = 72 * (30.4ma) 2 = 6.47mw per output ? dynamic power dissipation at 25mhz power (25mhz) = c pd * frequency * (v ddo_cmos ) 2 = 8pf * 25mhz * (3.465v) 2 = 2.4 mw total power dissipation ? total power = power (core, lvds) + total power (r out ) + total power (125mhz) + total power (25mhz) = 572mw + 6.47mw + 2.4mw = 581mw
idt ? / ics ? insert product name 13 ics844001ag-21 rev. a september 14, 2007 ics844001-21 femtoclocks? crystal-to-l vds frequency synthesizer preliminary 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks tm devices is 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 82.3c/w per table 7 is: 70c + 0.581w * 82.3c/w = 118c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow , and the type of board (single layer or multi-layer). ja by velocity (meters per second) 0 1 2.5 multi-layer pcb, jedec standard test boards 82.3c/w 78c/w 75.9c/w t able 7. t hermal r esistance ja for 24-tssop, f orced c onvection
idt ? / ics ? insert product name 14 ics844001ag-21 rev. a september 14, 2007 ics844001-21 femtoclocks? crystal-to-l vds frequency synthesizer preliminary r eliability i nformation t ransistor c ount the transistor count for ics844001-21 is: 4045 t able 8. ja vs . a ir f low t able for 24 l ead tssop ja by velocity (meters per second) 0 1 2.5 multi-layer pcb, jedec standard test boards 82.3c/w 78c/w 75.9c/w
idt ? / ics ? insert product name 15 ics844001ag-21 rev. a september 14, 2007 ics844001-21 femtoclocks? crystal-to-l vds frequency synthesizer preliminary p ackage o utline - g s uffix for 24 l ead tssop t able 9. p ackage d imensions reference document: jedec publication 95, mo-153 l o b m y s s r e t e m i l l i m m u m i n i mm u m i x a m n4 2 a- -0 2 . 1 1 a5 0 . 05 1 . 0 2 a0 8 . 05 0 . 1 b9 1 . 00 3 . 0 c9 0 . 00 2 . 0 d0 7 . 70 9 . 7 ec i s a b 0 4 . 6 1 e0 3 . 40 5 . 4 ec i s a b 5 6 . 0 l5 4 . 05 7 . 0 0 8 a a a- -0 1 . 0
idt ? / ics ? insert product name 16 ics844001ag-21 rev. a september 14, 2007 ics844001-21 femtoclocks? crystal-to-l vds frequency synthesizer preliminary while the information presented herein has been checked for both accuracy and reliability, integrated device technology, incorp orated (idt) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or l icenses are implied. this product is intended for use in normal commercial applications. any other applications such as those requiring extended termperature ranges, high reliability or other extraordi nary environmental requirements are not recommended without additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not authorize or w arrant any idt product for use in life support devices or critical medical instruments. t able 10. o rdering i nformation r e b m u n r e d r o / t r a pg n i k r a me g a k c a pg n i g a k c a p g n i p p i h se r u t a r e p m e t 1 2 - g a 1 0 0 4 4 8 s c i1 2 g a 1 0 0 4 4 8 s c ip o s s t d a e l 4 2e b u tc 0 7 o t c 0 t 1 2 - g a 1 0 0 4 4 8 s c i1 2 g a 1 0 0 4 4 8 s c ip o s s t d a e l 4 2l e e r & e p a t 0 0 5 2c 0 7 o t c 0 f l 1 2 - g a 1 0 0 4 4 8 s c id b tp o s s t " e e r f d a e l " d a e l 4 2e b u tc 0 7 o t c 0 t f l 1 2 - g a 1 0 0 4 4 8 s c id b tp o s s t " e e r f d a e l " d a e l 4 2l e e r & e p a t 0 0 5 2c 0 7 o t c 0 . t n a i l p m o c s h o r e r a d n a n o i t a r u g i f n o c e e r f - b p e h t e r a r e b m u n t r a p e h t o t x i f f u s " f l " n a h t i w d e r e d r o e r a t a h t s t a p : e t o n
innovate with idt and accelerate your future networks. contact: www.idt.com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support netcom@idt.com 480-763-2056 corporate headquarters integrated device t echnology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) asia pacific and japan integrated device technology singapore (1997) pte. ltd. reg. no. 199707558g 435 orchard road #20-03 wisma atria singapore 238877 +65 6 887 5505 europe idt europe, limited 321 kingston road leatherhead, surrey kt22 7tu england +44 (0) 1372 363 339 fax: +44 (0) 1372 378851 ? 2007 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt, th e idt logo, ics and hiperclocks are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other br ands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa ics844001-21 femtoclocks? crystal-to-l vds frequency synthesizer preliminary

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